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1 ? fn4519.6 HC55180, hc55181, hc55183, hc55184 extended reach ringing slic family the rslic18 family of ringing subscriber line interface circuits (rslic) supports analog plain old telephone service (pots) in short and medium loop le ngth, wireless and wireline applications. ideally suited for re mote subscriber units, this family of products offers fl exibility to designers with high ringing voltage and low power consumption system requirements. the rslic18 family operates to 100v which translates directly to the amount of ringing voltage supplied to the end subscriber. with the high operati ng voltage, subscriber loop lengths can be extended to 500 ? (i.e., 5,000 feet) and beyond. other key features across the product family include: low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detec tion mechanisms for when subscribers go on or off hook, and minimal external discrete application components. integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests. there are five product offeri ngs in the rslic18 family: HC55180, hc55181, hc55183 and hc55184. the architecture for this family is based on a voltage feed amplifier design using low fixed loop gains to achieve high analog performance with lo w susceptibility to system induced noise. block diagram features ? battery operation to 100v ? low standby power consumption of 50mw ? peak ringing amplitude 95v, 5 ren ? sinusoidal or trapezoidal ringing capability ? integrated codec ringing interface ? integrated mtu dc characteristics ? low external component count ? pulse metering and on hook transmission ? tip open ground start operation ? thermal shutdown with alarm indicator ? 28 lead surface mount packaging ? dielectric isolated (di) high voltage design ? HC55180 - silent polarity reversal - 53db longitudinal balance - loopback test capability ? hc55181 - integrated battery switch - silent polarity reversal - 53db longitudinal balance - loopback and test access capability ? hc55183 - integrated battery switch - 45db longitudinal balance ? hc55184 - integrated battery switch - silent polarity reversal - 45db longitudinal balance applications ? wireless local loop (wll) ? digital added main line (daml)/pairgain ? integrated services digital network (isdn) ? small office home office (soho) pbx ? cable/computer telephony related literature ? an9814, user?s guide for development board ? an9824, modeling of the ac loop ? an tbd, interfacing to dsp codecs vrs vrx vtx -in vfb f2 f1 f0 ilim tip ring sw+ sw- rtd rd det alm ringing port 4-wire port control logic battery switch transmit sensing detector logic dc control 2-wire port test access e0 pol cdc vbh vbl bsel swc data sheet july 2003 caution: these devices are sensitive to electrostati c discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. all other trademarks mentioned are the property of their respecti ve owners. rslic18? is a trademark of intersil corporation. n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t h c 5 5 1 8 5
2 ordering information (plcc package only) part number 100v 85v bat sw pol rev full test loop back only lb = 53db lb = 58db temp. range ( o c) package package no. HC55180dim ? ? ? ? -40 to 85 28 ld plcc n28.45 hc55181dim ? ? ? ? ? -40 to 85 28 ld plcc n28.45 hc55183ecm 75v ? 45db 0 to 70 28 ld plcc n28.45 hc55184ecm 75v ? ? 45db 0 to 70 28 ld plcc n28.45 hc5518xeval1 evaluation board platform, including codec. device operating modes operating mode f2 f1 f0 e0 = 1 e0 = 0 description HC55180 hc55181 hc55183 hc55184 low power standby 0 0 0 shd gkd mtu compliant standby mode with active loop detector. ? ? ? ? forward active 0 0 1 shd gkd forward battery loop feed. ? ? ? ? unused 0 1 0 n/a n/a this is a reserved internal test mode. reverse active 0 1 1 shd gkd reverse battery loop feed. ? ? ? ringing 1 0 0 rtd rtd balanced ringing mode supporting both sinusoidal, trapezoidal and ringing waveforms with dc offset. ? ? ? ? forward loop back 1 0 1 shd gkd internal device test mode. ? ? tip open 1 1 0 shd gkd tip amplifier disabled and ring amplifier enabled. intended for pbx type applications. ? ? power denial 1 1 1 n/a n/a device shutdown. ? ? ? ? HC55180, hc55181, hc55183, hc55184
3 pinout HC55180 (plcc) top view hc55181 (plcc) top view hc55183 (plcc) top view hc55184 (plcc) top view ring ilim rtd cdc vrx vrs pol nc bsel rd -in vfb vcc vtx bgnd tip sw- e0 det alm agnd sw+ vbl vbh swc f2 f1 f0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 ring ilim rtd cdc vrx vrs pol nc bsel rd -in vfb vcc vtx bgnd tip sw- e0 det alm agnd sw+ vbl vbh swc f2 f1 f0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 ring ilim rtd cdc vrx vrs nc nc bsel rd -in vfb vcc vtx bgnd tip nc e0 det alm agnd nc vbl vbh nc f2 f1 f0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 ring ilim rtd cdc vrx vrs pol nc bsel rd -in vfb vcc vtx bgnd tip nc e0 det alm agnd nc vbl vbh nc f2 f1 f0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 HC55180, hc55181, hc55183, hc55184
4 absolute m aximum ratings t a = 25 o c thermal information maximum supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v v cc - v bat (180, 181) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110v v cc - v bat (183, 184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85v uncommitted switch voltage . . . . . . . . . . . . . . . . . . . . . . . -110v maximum tip/ring negative voltage pulse (note 18). . . . . . . -115v maximum tip/ring positive voltage pulse (note 18) . . . . . . . . . .8v esd (human body model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500v operating conditions temperature range industrial (i suffix) . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c commercial (c suffix) . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c positive power supply (v cc ). . . . . . . . . . . . . . . . . . . . . . . +5v 5% negative power supply (v bh , v bl ) (180, 181) . . . . . -16v to -100v negative power supply (v bh , v bl ) (183, 184) . . . . . . -24v to -75v uncommitted switch (loop back or relay driver) . . . . . +5v to -100v thermal resistance (typical, note 1) ja ( o c/w) plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 maximum junction temperature plastic . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (plcc - lead tips only) die characteristics substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v bat process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications unless otherwise specified, t a = 0 o c to 70 o c for the hc55183, 184 only, all others -40 o c to 85 o c, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are specified at 600 ? 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. parameter test conditions min typ max units ringing parameters (note 2) vrs input impedance (note 3) 480 - - k ? differential ringing gain vrs to 2-wire, r load = (note 4) 78 80 82 v/v 4-wire to 2-wire ringing off isolation active mode, referenced to vrs input. - 60 - db 2-wire to 4-wire transmit isolation ringing mode referenced to the differential ringing amplitude. - 60 - db ac transmission parameters (notes 5, 6) receive input impedance (note 3) 160 - - k ? transmit output impedance (note 3) - - 1 ? 4-wire port overload level thd = 1% 3.1 3.5 - v pk 2-wire port overload level thd = 1% 3.1 3.5 - v pk 2-wire return loss f = 300hz - 26 - db f = 1khz - 32 - db f = 2.3khz - 21 - db f = 3.4khz - 17 - db longitudinal current capability (per wire) (note 3) test for false detect 20 - - ma rms test for false detect, low power standby 10 - - ma rms 4-wire to 2-wire insertion loss -0.20 0.0 +0.30 db 2-wire to 4-wire insertion loss -6.22 -6.02 -5.82 db 4-wire to 4-wire insertion loss -6.32 -6.02 -5.82 db idle channel noise 2-wire c-message - 16 19 dbrnc psophometric - -73.5 -71 dbmp idle channel noise 4-wire c-message - 10 13 dbrnc psophometric - -79.5 -77 dbmp HC55180, hc55181, hc55183, hc55184
5 dc parameters (note 6) loop current limit programming range (note 5) max low battery = -52v 15 - 45 ma loop current during low power standby forward polarity only. 18 - 26 ma loop detectors and supervisory functions switch hook programming range 5 - 15 ma switch hook programming accuracy assumes 1% external programming resistor - 2 10 % dial pulse distortion - 1.0 - % ring trip comparator threshold 2.4 2.7 3.0 v ring trip programming current accuracy - - 10 % ground key threshold - 12 - ma thermal alarm output ic junction temperature - 175 - o c logic inputs (f0, f1, f2, e0, swc, bsel) input low voltage - - 0.8 v input high voltage 2.0 - - v input low current v il = 0.4v -20 - - a input high current v ih = 2.4v - - 5 a logic outputs ( det , alm ) output low voltage i ol = 5ma - - 0.4 v output high voltage i oh = 100 a 2.4 - - v power supply rejection ratio v cc to 2-wire f = 300hz - 40 - db f = 1khz - 35 - db f = 3.4khz - 28 - db v cc to 4-wire f = 300hz - 45 - db f = 1khz - 43 - db f = 3.4khz - 33 - db v bl to 2-wire 300hz f 3.4khz - 30 - db v bl to 4-wire 300hz f 3.4khz - 35 - db v bh to 2-wire 300hz f 3.4khz - 33 - db v bh to 4-wire 300hz f 1khz - 40 - db 1khz < f 3.4khz - 45 - db notes: 2. these parameters are specified at high battery operation. for t he HC55180 the external supply is set to high battery voltage, f or the hc55181, hc55183 and hc55184, bsel = 1. 3. these parameters are controlled via design or process parameters and are not directly tested. these parameters are characterize d upon initial design release and upon design changes which would affect these characteristics. 4. differential ringing gain is measured with vrs = 0.795 v rms for -100v devices, vrs = 0.663 v rms for -85v devices and vrs = 0.575 v rms for -75v devices. 5. these parameters are specified at low battery operation. for the HC55180, the external supply is set to low battery voltage, fo r the hc55181, hc55183 and hc55184, bsel = 0. 6. forward active and reverse active per formance is guaranteed for the HC55180, hc55181 and hc55184 devices only. the hc55183 is specified for forward active operation only. electrical specifications unless otherwise specified, t a = 0 o c to 70 o c for the hc55183, 184 only, all others -40 o c to 85 o c, v bl = -24v, v bh = -100v, -85v or -75v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are specified at 600 ? 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. (continued) parameter test conditions min typ max units HC55180, hc55181, hc55183, hc55184
6 HC55180, hc55181, hc55183, hc55184 electrical specifications unless otherwise specified, t a = 0 o c to 70 o c for the hc55183, 184 only, all others -40 o c to 85 o c, v bl = -24v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are specified at 600 ? 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . parameter HC55180 (note 7) hc55181 hc55183, hc55184 units test conditions min typ max test conditions min typ max test conditions min typ max ringing parameters (note 2) ringing voltage open circuit (note 8) thd 0.5% v b = -85v - 80 - thd 0.5% v bh = -85v 80 - - thd 0.5% v bh = -75v 70 - - v peak thd 0.5% v b = -100v - 95 - thd 0.5% v bh = -100v 95 - - (note 9) - - - v peak ringing voltage load = 1.3k (notes 8, 10) thd 3.0% v b = -85v - 80 - thd 3.0% v bh = -85v 80 - - thd 3.0% v bh = -75v 70 - - v peak thd 3.0% v b = -100v - 95 - thd 3.0% v bh = -100v 95 - - (note 9) - - - v peak tip centering voltage v b = -85v, r l = - 2.5 - v bh = -85v, r l = - - 2.5 v bh = -75v, r l = - - 3 v v b = -100v, r l = - 2.0 - v bh = -100v, r l = - - 2.0 (note 9) - - - v ring centering voltage v b = -85v, r l = - 2.5 - v bh = -85v, r l = - - 2.5 v bh = -75v, r l = - - 3 v v b = -100v, r l = - 2.0 - v bh = -100v, r l = - - 2.0 (note 9) - - - v ac transmission parameters (notes 5, 6) 2-wire longitudinal balance (notes 12, 13) (note 11) - - - - - - grade e 45 53 - db grade c, d - 59 - grade c, d 53 59 - (note 11) - - - db 4-wire longitudinal balance (note 11) - - - - - - grade e - 58 - db grade c, d - 64 - grade c, d - 64 - (note 11) - - - db 2-wire to 4-wire level linearity 4-wire to 2-wire level linearity referenced to -10dbm +3 to -40dbm, 1khz - 0.02 5 - +3 to -40dbm, 1khz - 0.025 - +3 to -40dbm, 1khz - 0.02 5 - db -40 to -50dbm, 1khz - 0.05 0 - -40 to -50dbm, 1khz - 0.050 - -40 to -50dbm, 1khz - 0.05 0 - db -50 to -55dbm, 1khz - 0.10 0 - -50 to -55dbm, 1khz - 0.100 - -50 to -55dbm, 1khz - 0.10 0 - db dc parameters loop current accuracy (notes 5, 6) i l = 25ma - - 8.5 i l = 25ma - - 8.5 i l = 25ma - - 10 % open circuit voltage (|tip - ring|, note 6) v b = -16v - 7.5 - v bl = -16v 6.0 7.5 9.0 v bl = -16v - 7.5 - v v b = -24v 14 15.5 17 v bl = -24v 14 15.5 17 v bl = -24v 14 15.5 17 v v b > -60v 43 50 - v bh = -60v, bsel = 1 43 50 - v bh = -60v, bsel = 1 43 50 - v
7 low power standby open circuit voltage (tip - ring, note 2) v b = -48v 43 47 - v bh = -48v 43 - 47 v bh = -48v 43 - 47 v v b > -60v 43 49 - v bh = -60v, bsel = 1 43 49 - v bh = -60v, bsel = 1 43 49 - v absolute open circuit voltage (note 6) v rg in lps and fa v tg in ra v b > -60v - -53 -56 v rg in lps and fa v tg in ra v bh = -60v, bsel = 1 - -53 -56 v rg in lps and fa v tg in ra v bh = -60v, bsel = 1 - -53 -56 v test access functions switch on voltage (note 14) - - - i ol = 45ma - 0.30 0.60 (note 14) - - - v loopback max battery - - 52 - - 52 (note 15) - - 52 v supply currents (supply currents not listed are considered negligible and do not contribute significantly to total power dissipation. all measu rements made under open circuit load conditions.) low power standby (note 2) i cc 2.0 3.7 6.0 i cc 2.0 3.7 6.0 i cc - 3.7 6.0 ma i b , v b = -100v, -85v - 0.375 0.600 i bh , v bh = -100v, -85v - 0.375 0.600 i bh , v bh = -75v - 0.375 - ma forward or reverse (note 5) i cc 2.5 4.0 5.0 i cc 2.5 4.0 5.0 i cc 2.0 4.0 6.0 ma i b , v b = -24v - 1.0 2.5 i bl - 1.0 2.5 i bl - 1.0 2.5 ma forward (note 2) i cc 3.5 5.5 8.0 i cc 3.5 5.5 8.0 i cc 2.0 5.5 8.0 ma (note 7) - - - i bl - 1.3 2.0 i bl - 1.3 2.5 ma i b , v b = -100v, -85v - 3.2 4.5 i bh , v bh = -100v, -85v - 1.7 2.5 i bh , v bh = -75v - 1.4 3.0 ma ringing (note 2) i cc - 8.5 - i cc - 8.5 - i cc - 8.5 - ma (note 7) - - - i bl - 0.4 2.0 i bl - 0.4 2.0 ma i b , v b = -100v, -85v - 2.3 5.0 i bh , v bh = -100v, -85v - 1.3 2.5 i bh , v bh = -75v - 1.3 2.5 ma forward loopback (note 5) i cc - 8.5 10.0 i cc - 8.5 10.0 (note 15) - - - ma i b , v b = -24v - 19 25.5 i bl - 19 25.5 - - - ma tip open (note 5) i cc - - 5.5 i cc - - 5.5 (note 16) - - - ma i b , v b = -24v - - 1.0 i bl - - 1.0 - - - ma power denial (note 5) i cc 0.5 3.0 6.0 i cc 0.5 3.0 6.0 i cc - 3.0 6.0 ma i b , v b = -24v - 0.2 0.5 i bl - 0.2 0.5 i bl - 0.2 0.5 ma on hook power dissipation (note 17) forward or reverse (notes 5, 6) v b = -24v - 44 60 v bl = -24v - 44 60 v bl = -24v - 44 60 mw electrical specifications unless otherwise specified, t a = 0 o c to 70 o c for the hc55183, 184 only, all others -40 o c to 85 o c, v bl = -24v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are specified at 600 ? 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . (continued) parameter HC55180 (note 7) hc55181 hc55183, hc55184 units test conditions min typ max test conditions min typ max test conditions min typ max HC55180, hc55181, hc55183, hc55184
8 low power standby (note 2) v b = -85v - 52 - v bh = -85v - 52 75 v bh = -75v - 46 70 mw v b = -100v - 59 - v bh = -100v - 59 80 (note 9) - - - mw ringing (note 2) v b = -85v - 190 - v bh = -85v - 190 300 v bh = -75v - 170 275 mw v b = -100v - 220 - v bh = -100v - 220 325 (note 9) - - - mw off hook power dissipation (notes 5, 17) forward or reverse v b = -24v - 290 - v bl = -24v - 290 310 v bl = -24v - 280 310 mw notes: 7. the HC55180 does not provide battery switch operation. ther efore all battery voltage references will be made to v b . v b is the voltage applied to the common connection of the device v bl and v bh pins. see the HC55180 basic application circuit. 8. ringing voltage is measured with vrs = 0.839 v rms for -100v devices, vrs = 0.707 v rms for -85v devices and vrs = 0.619 v rms for -75v devices. all measurements are at t = 25 o c. 9. the hc55183 and hc55184 devices are specified with a single high battery voltage grade. 10. the device represents a low output impedance during ringing. therefore the voltage acro ss the ringing load is determined by the voltage divider formed by the protection resistance, loop resistance and ringing load impedance. 11. the HC55180, hc55183 and hc55184 are specified with a single longitudinal balance grade. 12. longitudinal balance is tested per ieee455-1985, with 368 ? per tip and ring terminal. 13. these parameters are tested 100% at room temperature. these pa rameters are guaranteed not tested across temperature via statist ical characterization. 14. the HC55180, hc55183 and hc55184 do not support uncommitted switch operation. 15. the hc55183 and hc55184 do not support the forward loopback operating mode. 16. the hc55183 and hc55184 do not support the tip open operating mode. 17. the power dissipation numbers are actual dev ice measurements and will be less than wors e case calculations based on data sheet supply current limits. 18. characterized with 2 x 10 s, and 10 x 1000 s first level lightning surge waveforms (gr-1089-core). electrical specifications unless otherwise specified, t a = 0 o c to 70 o c for the hc55183, 184 only, all others -40 o c to 85 o c, v bl = -24v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are specified at 600 ? 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . (continued) parameter HC55180 (note 7) hc55181 hc55183, hc55184 units test conditions min typ max test conditions min typ max test conditions min typ max HC55180, hc55181, hc55183, hc55184
9 design equations loop supervision thresholds switch hook detect the switch hook detect threshold is set by a single external resistor, r sh . equation 1 is used to calculate the value of r sh . the term i sh is the desired dc loop current threshold. the loop current threshold programming range is from 5ma to 15ma. ground key detect the ground key detector senses a dc current imbalance between the tip and ring terminals when the ring terminal is connected to ground. the ground key detect threshold is not externally programmable and is internally fixed to 12ma regardless of the switch hook threshold. ring trip detect the ring trip detect threshold is set by a single external resistor, r rt . i rt should be set between the peak ringing current and the peak off hook current while still ringing. the capacitor c rt , in parallel with r rt , will set the ring trip response time. loop current limit the loop current limit of the device is programmed by the external resistor r il . the value of r il can be calculated using equation 3. the term i lim is the desired loop current limit. the loop current limit programming range is from 15ma to 45ma. impedance matching the impedance of the device is programmed with the external component r s . r s is the gain setting resistor for the feedback amplifier that provides impedance matching. if complex impedance matching is required, then a complex network can be substituted for r s . resistive impedance synthesis the source impedance of the device, z o , can be calculated in equation 4. the required impedance is defined by the terminating impedance and protection resistors as shown in equation 5. 4-wire to 2-wire gain the 4-wire to 2-wire gain is defined as the receive gain. it is a function of the terminati ng impedance, synthesized impedance and protection resist ors. equation 6 calculates the receive gain, g 42 . when the device source impe dance and protection resistors equals the terminating impedance, the receive gain equals unity. 2-wire to 4-wire gain the 2-wire to 4-wire gain (g 24 ) is the gain from tip and ring to the vtx output. the transmit gain is calculated in equation 7. when the protection resistors are set to zero, the transmit gain is -6db. transhybrid gain the transhybrid gain is defined as the 4-wire to 4-wire gain (g 44 ). when the protection resistors ar e set to zero, the transhybrid gain is -6db. complex impedance synthesis substituting the impedance programming resistor, r s , with a complex programming network provides complex impedance synthesis. the reference designators in the programming network match the evaluation board. the component r s has a different design equ ation than the r s used for resistive impedance synthesis. the design equations for each component are provided below. r sh 600 i sh ? = (eq. 1) r rt 1800 i rt ? = (eq. 2) r il 1760 i lim ------------ - = (eq. 3) r s 400 z o () = (eq. 4) z o z l 2r p ? = (eq. 5) g 42 2 z l z o + 2r p + z l ----------------------------------------- - ?? ?? ?? ? = (eq. 6) g 24 z o z o + 2r p + z l ----------------------------------------- - ?? ?? ?? ? = (eq. 7) g 44 z o z o 2r p z l ++ -------------------------------------- - ?? ?? ?? ? = (eq. 8) figure 1. complex programming network 2-wire network r 1 r 2 c 2 programming network r s r p c p r s 400 r 1 2r p () ? () = (eq. 9) r p 400 r 2 = (eq. 10) c p c 2 400 ? = (eq. 11) HC55180, hc55181, hc55183, hc55184
10 low power standby overview the low power standby mode (lps, 000) should be used during idle line conditions. the device is designed to operate from the high battery during this mode. most of the internal circuitry is powered down, resulting in low power dissipation. if the 2-wire (tip/ring) dc voltage requirements are not critical during idle line conditions, the device may be operated from the low batter y. operation from the low battery will decrease the standby power dissipation. 2-wire interface during lps, the 2-wire interface is maintained with internal switches and voltage references. the tip and ring amplifiers are turned off to conserve power. the device will provide mtu compliance, loop cu rrent and loop supervision. figure 2 represents the internal circuitry providing the 2-wire interface during low power standby. mtu compliance maintenance termination unit or mtu compliance places dc voltage requirements on the 2-wire terminals during idle line conditions. the minimum idle voltage is 42.75v. the high side of the mtu range is 56v. the voltage is expressed as the difference between tip and ring. the tip voltage is held near ground through a 600 ? resistor and switch. the ring voltage is limited to a maximum of -49v (by mtu ref) when operat ing from either the high or low battery. a switch and 600 ? resistor connect the mtu reference to the ring terminal. when the high battery voltage exceeds the mtu referenc e of -49v (typically), the ring terminal will be clamped by the internal reference. the same ring relationships apply when operating from the low battery voltage. for high battery voltages (vbh) less than or equal to the internal mtu reference threshold: loop current during lps, the device will pr ovide current to a load. the current path is through resistors and switches, and will be function of the off hook loop resistance (r loop ). this includes the off hook phone resistance and copper loop resistance. the current available during lps is determined by equation 13. internal current limiting of the standby switches will limit the maximum current to 20ma. another loop current related parameter is longitudinal current capability. the longitudinal current capability is reduced to 10ma rms per pin. the reduction in longitudinal current capability is a result of turning off the tip and ring amplifiers. on hook power dissipation the on hook power dissipation of the device during lps is determined by the operating voltages and quiescent currents and is calculated using equation 14. the quiescent current terms are specified in the electrical tables for each operating mode. load power dissipation is not a factor since this is an on hook mode. some applications may specify a standby current. the standby current may be a charging current required for modern telephone electronics. standby current power dissipation any standby line current, i slc , introduces an additional power dissipation term p slc . equation 15 illustrates the power contribution is zero wh en the standby line current is zero. if the battery voltage is less than -49v (the mtu clamp is off), the standby line current power contribution reduces to equation 16. most applications do not specify charging current requirements during standby. w hen specified, the typical charging current may be as high as 5ma . table 1. device interfaces during lps interface on off notes receive x ac transmission, impedance matching and ringing are disabled during this mode. ringing x transmit x 2-wire x amplifiers disabled. loop detect x switch hook or ground key. figure 2. lps 2-wire interface circuit diagram tip amp ring amp tip ring mtu ref gnd 600 ? 600 ? v ring v bh 4 + = (eq. 12) i loop 1 ? 49 ? () ? () 600 600 r loop ++ () ? = (eq. 13) p lps v bh i bhq v bl i blq v cc i ccq ++ = (eq. 14) p slc i slc v bh 49 ? 1i slc x1200 ++ () = (eq. 15) p slc i slc v bh 1i slc x1200 ++ () = (eq. 16) HC55180, hc55181, hc55183, hc55184
11 forward active overview the forward active mode (fa, 001) is the primary ac transmission mode of the device. on hook transmission, dc loop feed and voice transmission are supported during forward active. loop supervision is provided by either the switch hook detector (e0 = 1) or the ground key detector (e0 = 0). the device may be operated from eit her high or low battery for on- hook transmission and low battery for loop feed. on-hook transmission the primary purpose of on hook transmission will be to support caller id and other advanced signalling features. the transmission over load level while on hook is 3.5v peak . when operating from the high bat tery, the dc voltages at tip and ring are mtu compliant. the typical tip voltage is -4v and the ring voltage is a function of the battery voltage for battery voltages less than -60v as shown in equation 17. loop supervision is provided by the switch hook detector at the det output. when det goes low, the low battery should be selected for dc loop feed and voice transmission. feed architecture the design implements a voltage feed current sense architecture. the device controls the voltage across tip and ring based on the sensing of load current. resistors are placed in series with tip and ring outputs to provide the current sensing. the diagram below illustrates the concept. by monitoring the current at th e amplifier output, a negative feedback mechanism sets the output voltage for a defined load. the amplifier gains are set by resistor ratios (r a , r b , r c ) providing all the perfor mance benefits of matched resistors. the internal sense resistor, r cs , is much smaller than the gain resistors and is typically 20 ? for this device. the feedback mechanism, k s , represents the amplifier configuration providin g the negative feedback. dc loop feed the feedback mechanism for monitoring the dc portion of the loop current is the loop dete ctor. a low pass filter is used in the feedback to block voice band signals from interfering with the loop current limit function. the pole of the low pass filter is set by the external capacitor c dc . the value of the external capacitor should be 4.7 f. most applications will operat e the device from low battery while off hook. the dc feed charac teristic of the device will drive tip and ring towards half battery to regulate the dc loop current. for light loads, tip will be near -4v and ring will be near v vbl + 4v. the following diagram shows the dc feed characteristic. the point on the y-axis labeled v tr(oc) is the open circuit tip to ring voltage and is defined by the feed battery voltage. the curve of figure 5 determi nes the actual loop current for a given set of loop conditions. the loop conditions are determined by the low battery voltage and the dc loop impedance. the dc loop impedance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook dc resistance. the slope of the feed characteri stic and the battery voltage define the maximum loop current on the shortest possible loop as the short circuit current i sc . the term i lim is the programmed current limit, 1760/r il . the line segment i a represents the constant current region of the loop current limit function. the maximum loop impedance for a programmed loop current is defined as r knee . v ring v bh 4 + = (eq. 17) figure 3. voltage feed current sense diagram + - + - v in v out r c r cs r l r b r a k s figure 4. dc feed characteristic m = ( ? v tr / ? i l ) = 10k ? i loop (ma) i lim v tr(oc) v tr , dc (v) v tr oc () v bl 8 ? = (eq. 18) figure 5. i loop vs r loop load characteristic r loop (? ) r knee i lim i loop (ma) i sc i a i b 2r p i sc i lim v tr oc () 2r p i lim ? 10k ----------------------------------------------------- - + = (eq. 19) i a i lim v tr oc () r loop i lim ? 10k -------------------------------------------------------------- + = (eq. 20) r knee v tr oc () i lim ------------------------ = (eq. 21) HC55180, hc55181, hc55183, hc55184
12 when r knee is exceeded, the device will transition from constant current feed to constant voltage , resistive feed. the line segment i b represents the resist ive feed portion of the load characteristic. voice transmission the feedback mechanism for monitoring the ac portion of the loop current consists of two amplifiers, the sense amplifier (sa) and the transmit amplifier (ta). the ac feedback signal is used for impedance synthesis. a detailed model of the ac feed back loop is provided below. the gain of the transmit amplifier, set by r s , determines the programmed impedance of the device. the capacitor c fb blocks the dc component of the loop current. the ground symbols in the model represent ac grounds, not actual dc potentials. the sense amp output voltage, v sa , as a function of tip and ring voltage and load is calculated using equation 23. the transmit amplifier provides the programmable gain required for impedance synthesis. in addition, the output of this amplifier interfaces to the codec transmit input. the output voltage is calculated using equation 24. once the impedance matching components have been selected using the design equ ations, the above equations provide additional insight as to the expected ac node voltages for a specific tip and ring load. transhybrid balance the final step in completing the impedance synthesis design is calculating the necessary gains for transhybrid balance. the ac feed back loop produces an echo at the v tx output of the signal injected at v rx . the echo must be cancelled to maintain voice quality. most applications will use a summing amplifier in the codec front end as shown below to cancel the echo signal. the resistor ratio, r f /r b , provides the final adjustment for the transmit gain, g tx . the transmit gain is calculated using equation 25. most applications set r f = r b , hence the device 2-wire to 4-wire equals the transmit gain. typically r b is greater than 20k ? to prevent loading of the device transmit output. the resistor ratio, r f /r a , is determined by the transhybrid gain of the device, g 44 . r f is previously defined by the transmit gain requirement and r a is calculated using equation 26. power dissipation the power dissipated by the device during on hook transmission is strictly a function of the quiescent currents for each supply voltage during forward active operation. off hook power dissipation is increased above the quiescent power dissipation by the dc load. if the loop length is less than or equal to r knee , the device is pr oviding constant current, i a , and the power dissipation is calculated using equation 28. if the loop length is greater than r knee , the device is operating in the constant voltage, resistive feed region. the power dissipated in this region is calculated using equation 29. i b v tr oc () r loop ------------------------ = (eq. 22) figure 6. ac signal transmission model tip ring + - -in vfb vrx vtx r r r r + - + - + - 1:1 20 20 0.75r 3r 3r 3r 3r r/2 8k r s c fb t a v sa v sa v t v r ? () ? 10 z l ------ = (eq. 23) v vtx v sa r s 8k ------- - ?? ?? ? = (eq. 24) figure 7. transhybrid balance interface + - r f r b r a hc5518x codec +2.4v rx out tx in -in vrx vtx r r + - 1:1 r s t a g tx g ? 24 r f r b ------- - ?? ?? ?? = (eq. 25) r a r b g 44 ---------- = (eq. 26) p faq v bh i bhq v bl i blq v cc i ccq ++ = (eq. 27) p fa ia () p fa q () v bl xi a () r loop xi 2 a () ? + = (eq. 28) p fa ib () p fa q () v bl xi b () r loop xi 2 b () ? + = (eq. 29) HC55180, hc55181, hc55183, hc55184
13 since the current relationship s are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations. reverse active overview the reverse active mode (ra, 011) provides the same functionality as the forward active mode. on hook transmission, dc loop feed and voice transmission are supported. loop supervision is pr ovided by either the switch hook detector (e0 = 1) or the ground key detector (e0 = 0). the device may be operated from either high or low battery. during reverse active the tip and ring dc voltage characteristics exchange roles. that is, ring is typically 4v below ground and tip is typically 4v more positive than battery. otherwise, all feed and voice transmission characteristics are identical to forward active. silent polarity reversal changing from forward active to reverse active or vice versa is referred to as polarity reversal. many applications require slew rate control of the polarity reversal event. requirements range from minimizing cross talk to protocol signalling. the device uses an external low voltage capacitor, c pol , to set the reversal time. once programmed, the reversal time will remain nearly constant over various load conditions. in addition, the reversal timing capac itor is isolated from the ac loop, therefore loop stability is not impacted. the internal circuitry used to se t the polarity re versal time is shown below. during forward active, the current from source i1 charges the external timing capacitor c pol and the switch is open. the internal resistor provides a clamping function for voltages on the pol node. during reverse active, the switch closes and i2 (roughly twice i1) pulls current from i1 and the timing capacitor. the current at the pol node provides the drive to a differential pair which controls the reversal time of the tip and ring dc voltages. where ? time is the required reversal time. polarized capacitors may be used for c pol . the low voltage at the pol pin and minimal voltage excursion 0.75v, are well suited to polarized capacitors. power dissipation the power dissipation equations for forward active operation also apply to the reverse active mode. ringing overview the ringing mode (rng, 100) provides linear amplification to support a variety of ringing waveforms. a programmable ring trip function provides loop supervision and auto disconnect upon ring trip. the device is designed to operate from the high battery during this mode. architecture the device provides linear amplif ication to the signal applied to the ringing input, v rs . the differential ringing gain of the device is 80v/v. the circuit model for the ringing path is shown in the following figure. the voltage gain from the vrs input to the tip output is 40v/v. the resistor ratio provid es a gain of 8 and the current mirror provides a gain of 5. the voltage gain from the vrs input to the ring output is -4 0v/v. the equations for the tip and ring outputs during ringing are provided below. when the input signal at vrs is zero, the tip and ring amplifier outputs are centered at half battery. the device provides auto centering fo r easy implementation of sinusoidal ringing waveforms. both ac and dc control of the tip and ring outputs is availabl e during ringing. this feature allows for dc offsets as part of the ringing waveform. ringing input the ringing input, v rs , is a high impedance input. the high impedance allows the use of low value capacitors for ac coupling the ring signal. the v rs input is enabled only during the ringing mode, therefor e a free running oscillator may be connected to vrs at all times. when operating from a battery of -100v, each amplifier, tip and ring, will swing a maximum of 95v p-p . hence, the maximum signal swing at vrs to achieve full scale ringing is figure 8. reversal timing control c pol pol i 1 75k ? i 2 c pol ? time 75000 ---------------- = (eq. 30) figure 9. linear ringing model tip ring vrs r/8 r r + - + - 5:1 20 20 + - + - 800k v bh 2 v t v bh 2 ----------- 40 vrs () + = (eq. 31) v r v bh 2 ----------- 40 vrs () ? = (eq. 32) HC55180, hc55181, hc55183, hc55184
14 approximately 2.4v p-p . the low signal levels are compatible with the output voltage range of the codec. the digital nature of the codec ideally su its it for the function of programmable ringing generator. see applications. logic control ringing patterns consist of silent intervals. the ringing to silent pattern is called the ri nging cadence. during the silent portion of ringing, the device can be programmed to any other operating mode. the most likely candidates are low power standby or forward ac tive. dependi ng on system requirements, the low or hi gh battery may be selected. loop supervision is provided with the ring trip detector. the ring trip detector senses the change in loop current when the phone is taken off hook. the loop detector full wave rectifies the ringing current, which is then filtered with external components r rt and c rt . the resistor r rt sets the trip threshold and the capacitor c rt sets the trip response time. most applications will require a trip response time less than 150ms. three very distinct actions o ccur when the devices detects a ring trip. first, the det output is latched low. the latching mechanism eliminates the need for software filtering of the detector output. the latch is cleared when the operating mode is changed externally. second, the vrs input is disabled, removing the ring signal from the line. third, the device is internally forced to the forward active mode. power dissipation the power dissipation during ringing is dictated by the load driving requirements and the ringing waveform. the key to valid power calculations is the correct definition of average and rms currents. the average current defines the high battery supply current. the rms current defines the load current. the cadence provides a time averaging reduction in the peak power. the total power dissipation consists of ringing power, p r , and the silent interval power, p s . the terms t r and t s represent the cadence. the ringing interval is t r and the silent interval is t s . the typical cadence ratio t r :t s is 1:2. the quiescent power of the device in the ringing mode is defined in equation 34. the total power during the ringing interval is the sum of the quiescent power and loading power: for sinusoidal waveforms, the average current, i avg , is defined in equation 36. the silent interval power dissipation will be determined by the quiescent power of th e selected operating mode. forward loop back overview the forward loop back mode (flb, 101) provides test capability for the device. an internal signal path is enabled allowing for both dc and ac verification. the internal 600 ? terminating resistor has a tolerance of 20%. the device is intended to operate from only the low battery during this mode. architecture when the forward loop back mode is initiated internal switches connect a 600 ? load across the outputs of the tip and ring amplifiers. dc verification when the internal signal path is provided, dc current will flow from tip to ring. the dc current will force det low, indicating the presence of loop current. in addition, the alm output will also go low. this does not indicate a thermal alarm condition. rather, proper logic operation is verified in the event of a thermal shutdown. in addition to verifying device functionality, toggling t he logic outputs verifies the interface to the system controller. ac verification the entire ac loop of the device is active during the forward loop back mode. therefore a 4- wire to 4-wire level test capability is provided. depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. system architectures which c annot disable the transhybrid function would require a two step process. the first step would be to send a test tone to the device while on hook and not in forward loop back mode. the return signal would be the test level times the gain r f /r a of the transhybrid amplifier. since the device would not be terminated, cancellation would not occur. the second step would be to program the device to flb and resend the test tone. the p rng p r t r t r t s + -------------- p s t s t r t s + -------------- + = (eq. 33) p rq () v bh i bhq v bl i blq v cc i ccq ++ = (eq. 34) p r p rq () v bh i avg v rms 2 z ren r loop + ------------------------------------------ ? + = (eq. 35) i avg 2 -- - ?? ?? v rms 2 z ren r loop + ------------------------------------------ = (eq. 36) figure 10. forward loop back internal termination ring amp tip amp ring tip 600 ? HC55180, hc55181, hc55183, hc55184
15 return signal would be much lower in amplitude than the first step, indicating the device was active and the internal termination attenuated the return signal. system architectures which dis able the transhybrid function would achieve test coverage with a signal step. once the transhybrid function is disable, program the device for flb and send the test tone. the return signal level is determined by the 4-wire to 4-wire gain of the device. tip open overview the tip open mode (110) is intended for compatibility for pbx type interfaces. used during idle line conditions, the device does not provide transm ission. loop supervision is provided by either the switch hook detector (e0 = 1) or the ground key detector (e0 = 0). the ground key detector will be used in most applications. the device may be operated from either high or low battery. functionality during tip open operation, the tip amplifier is disabled and the ring amplifier is enabled. the minimum tip impedance is 30k ? . the only active path through the device will be the ring amplifier. in keeping with the mtu characteristics of the device, ring will not exceed -56.5v when operating from the high battery. though mtu does not apply to tip open, safety requirements are satisfied. on hook power dissipation the on hook power dissipation of the device during tip open is determined by the operating voltages and quiescent currents and is calculated using equation 37. the quiescent current terms are specified in the electrical tables for each operating mode. load power dissipation is not a factor since this is an on hook mode. power denial overview the power denial mode (111) will shutdown the entire device except for the logic interfac e. loop supervision is not provided. this mode may be used as a sleep mode or to shut down in the presence of a persistent thermal alarm. switching between high and low battery will have no effect during power denial. functionality during power denial, both the tip and ring amplifiers are disabled, representing high impedances. the voltages at both outputs are near ground. thermal shutdown in the event the safe die temperature is exceeded, the alm output will go low and det will go high and the part will automatically shut down. when the device cools, alm will go high and det will reflect the loop status. if the thermal fault persists, alm will go low again and the part will shut down. programming power denial will permanently shutdown the device and stop t he self cooling cycling. battery switching overview the integrated battery switch selects between the high battery and low battery. the battery switch is controlled with the logic input bsel. when bsel is a logic high, the high battery is selected and when a logic low, the low battery is selected. all opera ting modes of the device will operate from high or low battery except forward loop back. functionality the logic control is independent of the operating mode decode. independent logic control provides the most flexibility and will support all application configurations. when changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. in most cases, this will minimize overall power dissipation and prevent glitches on the det output. the only external component required to support the battery switch is a diode in series with the v bh supply lead. in the event that high battery is re moved, the diode allows the device to transition to low battery operation. low battery operation all off hook operating conditions should use the low battery. the prime benefit will be reduced power dissipation. the typical low battery for the devi ce is -24v. however this may be increased to support longer loop lengths or high loop current requirements. standby conditions may also operate from the low battery if mtu compliance is not required, further reducing standby power dissipation. high battery operation other than ringing, the high battery should be used for standby conditions which must provide mtu compliance. during standby operation the power consumption is typically 50mw with -100v battery. if ringing requirements do not require full 100v operation, then a lower battery will result in lower standby power. high voltage decoupling the 100v rating of the device will require a capacitor of higher voltage rating for decoupling. suggested decoupling values for all device pins are 0.1 f. standard surface mount ceramic capacitors are rated at 100v. for applications driven at low cost and small size, the decoupling scheme shown below could be implemented. p to v bh i bhq v bl i blq v cc i ccq ++ = (eq. 37) HC55180, hc55181, hc55183, hc55184
16 as with all decoupling schemes , the capacitors should be as close to the device pins as physically possible. uncommitted switch overview the uncommitted switch is a three terminal device designed for flexibility. the independent logic control input, swc , allows switch operation regardless of device operating mode. the switch is activated by a logic low. the positive and negative terminals of the device are labeled sw+ and sw- respectively. relay driver the uncommitted switch may be used as a relay driver by connecting sw+ to the relay coil and sw- to ground. the switch is designed to have a maximum on voltage of 0.6v with a load current of 45ma. since the device provides the ringing waveform, the relay functions which may be supported include subscriber disconnect, test access or line interface bypass. an external snubber diode is not required when using the uncommitted switch as a relay driver. test load the switch may be used to connect test loads across tip and ring. the test loads can provide external test termination for the device. proper connection of the uncommitted switch to tip and ring is shown below. the diode in series with the test load blocks current from flowing through the uncommitted switch when the polarity of the tip and ring terminals are reversed. in addition to the reverse active state, the polarity of tip and ring are reversed for half of the ringing cycle. with independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the tip and ring terminals. figure 11. alternate decoupling scheme vbh vbl 0.22 0.22 hc5518x figure 12. external relay switching relay sw+ sw- swc +5v figure 13. test load switching ring tip test load sw+ sw- swc HC55180, hc55181, hc55183, hc55184
17 basic application circuit s vrx vrs tip vfb bgnd agnd vcc ring vtx -in vbl vbh rd rtd cdc ilim e0 f2 f1 f0 figure 14. HC55180 basic application circuit det alm HC55180 v cc pol c rx c rs c tx r il c fb r s r sh c rt r rt c pol c ps1 c dc c ps3 u 1 r p1 r p2 table 2. basic application circuit component list component value tolerance rating u1 - ringing slic hc5518x n/a n/a r rt 20k ? 1% 0.1w r sh 49.9k ? 1% 0.1w r il 71.5k ? 1% 0.1w r s 210k ? 1% 0.1w c rx , c rs , c tx , c rt , c pol , c fb 0.47 f 20% 10v c dc 4.7 f 20% 10v c ps1 0.1 f 20% >100v c ps2 , c ps3 0.1 f 20% 100v d 1 1n400x type with breakdown > 100v. r p1 , r p2 protection resistor values are application dependent and will be determined by protection requirements. standard applications will use 35 ? per side. design parameters : ring trip threshold = 90ma peak , switch hook threshold = 12ma, loop current limit = 24.6ma, synthesize device impedance = 210k ? /400 = 525 ? , with 39 ? protection resistors, impedance ac ross tip and ring terminals = 603 ? . where applicable, these component values apply to the basic appl ication circuits for the HC55180, hc55181, hc55183 and hc55184. pins not shown in the b asic application circuit are no connect (nc) pins. HC55180, hc55181, hc55183, hc55184
18 vrx vrs tip vfb bgnd agnd ring vtx -in sw+ sw- bsel rd rtd cdc ilim e0 f2 f1 f0 figure 15. hc55181 basic application circuit det alm hc55181 v cc pol swc c rx c rs c tx r il c fb r s r sh c rt r rt c pol c dc u 1 r p1 r p2 vcc vbl vbh d 1 c ps1 c ps3 c ps2 figure 16. hc55182 basic application circuit vrx vrs tip vfb bgnd agnd ring vtx -in bsel rd rtd cdc ilim e0 f2 f1 f0 det alm hc55183 v cc c rx c rs c tx r il c fb r s r sh c rt r rt c dc u 1 r p1 r p2 vcc vbl vbh d 1 c ps1 c ps3 c ps2 vrx vrs tip vfb bgnd agnd ring vtx -in bsel rd rtd cdc ilim e0 f2 f1 f0 figure 17. hc55184 basic application circuit det alm hc55184 v cc c rx c rs c tx r il c fb r s r sh c rt r rt c dc u 1 r p1 r p2 vcc vbl vbh d 1 c ps1 c ps3 c ps2 pol c pol HC55180, hc55181, hc55183, hc55184
19 additional applic ation diagrams reducing overhead voltages the transmission overhead voltage of the device is internally set to 4v per side. the overhead voltage may be reduced by injecting a negative dc voltage on the receive input using a voltage divider (figure 18). accordingly, the 2-wire port overload level will decrease the same amount as the injected offset. the divider shunt resistance is the parallel combination of the internal 160k ? resistor and the external r 2 . the sum of r 1 and r 2 should be greater than 500k ? to minimize the additional power dissipation of the divider. the dc gain relationship from the divider voltage, v d , to the tip and ring outputs is shown below. with a low battery voltage -24v and a divider voltage of -0.5v, the tip to ring voltage is 17v. as a result, the overhead voltage is reduced from 8v to 7v and the overload level will decrease from 3.5v peak to 3.0v peak . codec ringing generation maximum ringing amplitudes of the device are achieved with signal levels approximately 2.4v p-p . therefore the low pass receive output of the codec may serve as the low level ring generator. the ringing input impedance of 480k ? minimum should not interfere with codec drive capability. a single external capacitor is required to ac coupled the ringing signal from the codec. the circuit diagram for codec ringing is shown below. implementing tele tax signalling a resistor, r t , is required at the -in input of the device for injecting the teletax signal (figure 19). for most applications the synthesized device impedance (i.e., 600 ? ) will not match the 200 ? teletax impedance. the gain set by r t cancels the impedance matc hing feedback with respect to the teletax injection poin t. therefore the device appears as a low impedance source for teletax. the resistor r t is calculated using the following equation. the signal level across a 200 ? load will be twice the injected teletax signal level. as the teletax level at vtx will equal the injection level, set r c = r b for cancellation. the value of r b is based on the voice band transhybrid balance requirements. the connection of the teletax source to the transhybrid amplifier should be ac coupled to allow proper biasing of the transhybrid amplifier input ringing with dc offsets the balanced ringing waveform consists of zero dc offset between the tip and ring terminals. however, the linear amplifier architecture provides control of the dc offset during ringing. the dc gain is the same as the ac gain, 40v/v per amplifier. positive dc offsets applied directly to the ringing input will shift both tip and ring away from half battery towards ground and battery respectively. a voltage divider on the ringing input may be used to generate the offset (figure 21). the reference voltage, v ref , can be either the codec 2.4v reference voltage or the 5v supply. an offset during ringing of 30v, would require a dc shift of 15v at tip and 15v at ring. the dc offset would be created by a +0.375v (v d ) at the vrs input. the divider resistors should be selected to minimize the value of the ac coupling capacitor c rs and the loading of the ring generator and voltage reference. the ringing input impedance should also be accounted for in divider resistor calculations. figure 18. external overhead control hc5518x vbl from codec r 2 r 1 c rx v d 160k ? 1:1 vrx v tr ? v bl 82v d () ? ? = (eq. 38) figure 19. codec ringing interface hc5518x rx out codec 160k ? 1:1 vrs + - 480k vrx r t 200 200 2 r p r s 400 ? () ++ ------------------------------------------------------------------ - r s = (eq. 39) figure 20. teletax signalling + - r f r b codec +2.4v tx in -in vfb vtx + - rs cfb ta rt r c teletax source figure 21. external overhead control v ref from ring gen. r 2 r 1 c rs v d hc5518x vrs + - 480k HC55180, hc55181, hc55183, hc55184
20 pin descriptions plcc symbol description 1 tip tip power amplifier output. 2 bgnd battery ground - to be connected to zero potential. all l oop current and longitudinal current flow from this ground. internally separate from agnd but it is recommended t hat it is connected to the same potential as agnd. 3 vbl low battery supply connection. 4 vbh high battery supply connection for the most negative battery. 5 sw+ uncommitted switch positive terminal. this pi n is a no connect (nc) on the HC55180, hc55183 and hc55184. 6 sw- uncommitted switch negative terminal. this pin is a no connect (nc) on the HC55180, hc55183 and hc55184. 7 swc switch control input. this ttl compatible input controls th e uncommitted switch, with a logic ?0? enabling the switch and logic ?1? disabling the switch. this pin is a no connect (nc) on the HC55180, hc55183 and hc55184. 8 f2 mode control input - msb. f2-f0 for the ttl compatible paral lel control interface for controlling the various modes of operation of the device. 9 f1 mode control input. 10 f0 mode control input. 11 e0 detector output selection input. this ttl input controls the multiplexing of the shd (e0 = 1) and gkd (e0 = 0) comparator outputs to the det output based upon the state at the f2-f0 pi ns (see the device operating modes table shown on page page 2 ). 12 det detector output - this ttl output provides on-hook/off-hook status of the loop based upon the selected operating mode. the detected output will either be switch hook, ground key or ring trip (see the device operating modes table shown on page page 2 ). 13 alm thermal shutdown alarm. this pin signals the internal die temperature has exceeded safe operating temperature (approximately 175 o c) and the device has been powered down automatically. 14 agnd analog ground reference. this pin shou ld be externally connected to bgnd. 15 bsel selects between high and low battery, with a logic ?1? selecti ng the high battery and logic ?0? the low battery. this pin is a no connect (nc) on the HC55180. 16 nc this pin is a no connect ( nc) for all the devices. 17 pol external capacitor on this pin sets the polarity reversal time. this pin is a no connect on the hc55183. 18 vrs ringing signal input - analog input for driv ing 2-wire interface while in ring mode. 19 vrx analog receive voltage - 4-wire analog audio input voltage. ac couples to codec. 20 vtx transmit output voltage - output of impedance matching amplifier, ac couples to codec. 21 vfb feedback voltage for impedance matching. this voltag e is scaled to accomplish impedance matching. 22 -in impedance matching amplifier summing node. 23 vcc positive voltage power supply, usually +5v. 24 cdc dc biasing filter capacitor - connects between this pin and v cc . 25 rtd ring trip filter network. 26 ilim loop current limit programming resistor. 27 rd switch hook detection thres hold programming resistor. 28 ring ring power amplifier output. HC55180, hc55181, hc55183, hc55184
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HC55180, hc55181, hc55183, hc55184 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97

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